von Neumannovo schéma vjj 1 - PDF

Description
von Neumannovo schéma.0. vjj .0. vjj purpose: to execute instructions processor sample limitations: memory: AM + arithmetic register instructions with one address only constant instruction size (e.g. )

Please download to get full document.

View again

of 30
All materials on our website are shared by users. If you have any questions about copyright issues, please report us to resolve them. We are always happy to assist you.
Information
Category:

Novels

Publish on:

Views: 20 | Pages: 30

Extension: PDF | Download: 0

Share
Transcript
von Neumannovo schéma.0. vjj .0. vjj purpose: to execute instructions processor sample limitations: memory: AM + arithmetic register instructions with one address only constant instruction size (e.g. ) .0. vjj 3 instructions numbers: instruction code address load A A - add B + B - sub C - C - mpy B * B - div C / C - store D - D branch E next instruction is on address E .0. vjj 4 A = (B + C) * 0.98 example .0. vjj 0: load 0: add 03: sub 04: mpy 0: div 0: store 0: branch instructions .0. vjj 0: A 0: B 03: C 04: D 0: : $ 0: $ data .0. vjj code A = (B + C) * 0.98 LOAD STOE $ 0 0 LOAD C 0 03 STOE $ 0 0 LOAD B 0 0 $ 0 0 MPY $ 04 0 STOE A 0 0 .0. vjj 8 Von Neumann scheme AM 3 input 00 data register instruction register op. code addr micro-programs LOAD address register 4 instruction counter A + .0. vjj 9 mikroprograms load add sub save branch .0. vjj 0 AM 3 input 00 LOAD 4 LOAD + čítač instrukcí A + .0. vjj AM input 00 LOAD LOAD čítač instrukcí A + .0. vjj AM input 00 LOAD LOAD čítač instrukcí A + .0. vjj 3 AM input 00 LOAD LOAD čítač instrukcí A + .0. vjj 4 AM input 00 LOAD LOAD čítač instrukcí A + .0. vjj AM input 00 LOAD LOAD čítač instrukcí + A + .0. vjj AM input 00 LOAD LOAD čítač instrukcí A + .0. vjj AM input 00 LOAD LOAD čítač instrukcí A + .0. vjj 8 AM input 00 LOAD LOAD čítač instrukcí A + .0. vjj 9 AM input 00 LOAD čítač instrukcí A + .0. vjj AM 3 input 00 LOAD čítač instrukcí A + .0. vjj optimization micro-instructions merging golden rule: do not write and read value of any single memory unit in the same time .0. vjj optimization , , , , .0. vjj 3 AM 3 input 00 LOAD 4 LOAD čítač instrukcí A + .0. vjj 4 AM 3 input 00 LOAD 4 LOAD čítač instrukcí A + .0. vjj AM 3 input 00 LOAD 4 LOAD čítač instrukcí A + .0. vjj AM 3 input 00 LOAD 4 LOAD čítač instrukcí A + .0. vjj AM 3 input 00 LOAD 4 LOAD čítač instrukcí A + .0. vjj AM 3 input 00 LOAD čítač instrukcí A + .0. vjj 9 Von Neumann AM 3 input 00 LOAD 4 mikroprogramy čítač instrukcí A + .0. vjj ISC x CISC instruction sets reduced to replace the complete instruction set what for? to enable pipeline complete prior to ISC contemporary processors are using pipelines with complete set of instructions pipeline that's what the ISC processor has been devised for instructions are executed per partes (e.g. in phases: addresses calculation, arguments loading, execution, result saving, next instruction preparation) each instruction phase can be executed by a separate part of the processor -st part of the processor: instruction no. j+ -nd part of the processor: instruction no. j 3-rd part of the processor: instruction no. j-
Related Search
We Need Your Support
Thank you for visiting our website and your interest in our free products and services. We are nonprofit website to share and download documents. To the running of this website, we need your help to support us.

Thanks to everyone for your continued support.

No, Thanks